1st IEEE Inter. Symposium on Industrial Embedded Systems

Keynote: Models at Work; an industrially relevant keynote address ? Robert de Simone, INRIA Sophia-Antipolis, France.   Robert de Simonee INRIA Sophia-Antipolis, France.  Robert de Simone holds a PhD from Paris Jussieu University, defended in 1982. He is since 1984 with INRIA Sophia-Antipolis, as Junior then Senior Researcher. He is currently Scientific Leader of the Aoste project-team, which studies Methods and Models for the Analysis and the Optimization of Real-Time Embedded Systems. His interests range from  Concurrency Theory and Process Algebras, to Automatic Verification and model-checking tools, to Synchronous Languages and their semantics. Recently he has been working on Latency-Insensitive and GALS extensions to synchronous formalisms, and explicit Time representations for Models of Computations in a UML setting.  Dr de Simone has been involved in many academic and industrial contractual collaborations over the years. He leads INRIA's involvement in the French PACA Integrated Center for Microelectronics (CIM), together with many prominant industrial companies in the field. He is also INRIA coordinator on the forthcoming OMG UML profile for Modeling and Analysis of Real-Time Embedded systems (MARTE). ABSTRACT: We consider Models of  Computations as present  in many  graphical modeling formalisms often used in System-Level Embedded Design.We argue that these models should be well founded semantically if one aims to do more with them than mere simulation/animation, and  to perform useful analysis additionally instead. We try to illustrate this approach by considering progressive time refinement, from untimed to logically timed to eventually physically timed systems, using a collection of familiar models that share otherwise structural and behavioral aspects, but differ on their time handling precision. If time allows, we shall transform in this way a (trivially simple) synchronous SoC example to acommodate any long global wire latencies. It will depict the benefit of considering explicit logical time to represent time/cycle allocation schedules as first-class objects in the systems. If even more time is left,we shall present synchronous languages as specification/modeling formalisms where precise logical time is at the heart of the language itself. This allows to guarantee full adequacy between model simulaton and code synthesis/compilation, and consider the specification a true model of the system that runs.